1. Field of the Invention
This invention is related to the field of error correction codes (ECC).
2. Description of the Related Art
Various types of ECC schemes have been implemented in systems. For example, memory systems composed of random access memory (RAM) such as static RAM (SRAM), dynamic RAM (DRAM), etc. often implement ECC. In the memory system, storage is provided for the ECC-protected data and additional storage is provided for the ECC data. The ECC protects against errors that may be induced by failures in the memory, soft errors due to Alpha or Cosmic ray hits, etc.
In some systems, various interconnect may also be provided with ECC protection. Often, the ECC scheme used on the interconnect differs from the ECC scheme used in the memory. For example, the ECC scheme used in the memory typically generates each bit of ECC for a code word of data as a logical combination (e.g. exclusive OR, or XOR) of bits that are each stored in different memory chips, or modules, or banks, etc. In such a scheme, the failure of one chip, module, or bank may be detected and possibly corrected in addition to the possibility of detecting and correcting soft errors. The ECC scheme used on the interconnect may be as simple as parity, or may be an XOR scheme in which each ECC bit is generated from bits transmitted on different physical conductors or bits on the same conductor transmitted at different times. Furthermore, the ECC scheme used on one interconnect in a system may differ from the ECC scheme used on another interconnect in the same system.
Circuitry that bridges different ECC schemes, such as a memory controller or circuitry coupled to two interconnects having different ECC schemes, typically check that received data is error-free (using the ECC scheme corresponding to the transmitter of the data) and correct the received data, if needed. Prior to transmitting data to a receiver, the ECC is generated using the ECC scheme of the receiver to which the data is being transmitted.
Between the checking/correction of received data and generating ECC for transmitting data, the data is unprotected. As semiconductor manufacturing technologies have continued to decrease feature sizes, such as to 90 nanometer and below, the sensitivity of various storage devices such as flops to soft errors has begun to approach that of RAM memories. Accordingly, the rate of silent data corruption in flops and other such storage devices has been increasing to levels that are unacceptable for reliable system operation.